Difference between revisions of "BIOS Release Notes"
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== Napalm (Voodoo4 / Voodoo5) == | == Napalm (Voodoo4 / Voodoo5) == | ||
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<spoiler text="Version 0.01 (04/30/1999)"> | <spoiler text="Version 0.01 (04/30/1999)"> | ||
* Initial Version of Napalm BIOS. | * Initial Version of Napalm BIOS. | ||
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** Created the strings sz32768K and sz65536K. | ** Created the strings sz32768K and sz65536K. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.04 (05/11/1999)"> | <spoiler text="Version 0.04 (05/11/1999)"> | ||
* In the 32K ROM only, moved all the routines that are executed only during POST into the upper 32K of the ROM. These routines will be discarded after VGA POST s executed. | * In the 32K ROM only, moved all the routines that are executed only during POST into the upper 32K of the ROM. These routines will be discarded after VGA POST s executed. | ||
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** In tblExtRegisters, adjusted all the 1024x768 panel CR04, CR05, CR10, and CR11 settings to center the image on the panel. | ** In tblExtRegisters, adjusted all the 1024x768 panel CR04, CR05, CR10, and CR11 settings to center the image on the panel. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.07 (05/28/1999)"> | <spoiler text="Version 0.07 (05/28/1999)"> | ||
* Modified the VESA DDC EDID read routine to read DDC from the panel when active. | * Modified the VESA DDC EDID read routine to read DDC from the panel when active. | ||
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** Created the routine Patch32KROM to patch the ROM size when compiling a 32K ROM BIOS. | ** Created the routine Patch32KROM to patch the ROM size when compiling a 32K ROM BIOS. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.10 (06/23/1999)"> | <spoiler text="Version 0.10 (06/23/1999)"> | ||
* Fixed bug with some VGA modes not coming up on the TV. | * Fixed bug with some VGA modes not coming up on the TV. | ||
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** Renamed all the 18Xh mode numbers to 12Xh. Refer to the document MODELIST.DOC for mode numbers. | ** Renamed all the 18Xh mode numbers to 12Xh. Refer to the document MODELIST.DOC for mode numbers. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.15 (07/28/1999)"> | <spoiler text="Version 0.15 (07/28/1999)"> | ||
* Redefined the usage of the scratch registers. Made CR1E for TV data and CR1F for DFP data only. Defination of the scratch register usage is documented in "Scratch Register Usage.XLS". | * Redefined the usage of the scratch registers. Made CR1E for TV data and CR1F for DFP data only. Defination of the scratch register usage is documented in "Scratch Register Usage.XLS". | ||
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** Created the routine IsHalvedExtMode to return if we're a halved extende mode mode. | ** Created the routine IsHalvedExtMode to return if we're a halved extende mode mode. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.21 (10/11/1999)"> | <spoiler text="Version 0.21 (10/11/1999)"> | ||
* Merged in all the Napalm 0.20 changes onto the StarTeam Napalm BIOS. | * Merged in all the Napalm 0.20 changes onto the StarTeam Napalm BIOS. | ||
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** Created the null terminated strings for Chip name and BIOS Version. | ** Created the null terminated strings for Chip name and BIOS Version. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.24 (12/07/1999)"> | <spoiler text="Version 0.24 (12/07/1999)"> | ||
* Changed the panel CRTC timings to fix bug with setmode hanging while in a full screen DOS session in Win98. | * Changed the panel CRTC timings to fix bug with setmode hanging while in a full screen DOS session in Win98. | ||
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** Updated the copyright year to 2000. | ** Updated the copyright year to 2000. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.26a (01/12/2000)"> | <spoiler text="Version 0.26a (01/12/2000)"> | ||
* Changed device ID to 09h | * Changed device ID to 09h | ||
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** In InitRegisters, removed the DramInit0 mask to not clear DramInit0[26] | ** In InitRegisters, removed the DramInit0 mask to not clear DramInit0[26] | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.27 (01/15/2000)"> | <spoiler text="Version 0.27 (01/15/2000)"> | ||
* Create build options for Napalm board Assy# 879, 880, 881, 882, 883 and 884. | * Create build options for Napalm board Assy# 879, 880, 881, 882, 883 and 884. | ||
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** In DDCRead, placed a PUSH CX and POP CX around call to DDCWaitClockHigh. Fixed bug with a NACK never being sent to the monitor after reading the last byte of DDC data. This enables the BIOS to read DDC data from a Compaq FP720 DFP. | ** In DDCRead, placed a PUSH CX and POP CX around call to DDCWaitClockHigh. Fixed bug with a NACK never being sent to the monitor after reading the last byte of DDC data. This enables the BIOS to read DDC data from a Compaq FP720 DFP. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 0.30 (02/02/2000)"> | <spoiler text="Version 0.30 (02/02/2000)"> | ||
* Changed the name of the routine I2CReadByte to DFPReadByte. This routine now uses DDC calls to read DFP EDID data. This change fixes the problem with detecting scaled and non-scaled DFPs and also scaled DFPs now fully supported. Also fixes problem with scaled DFP not coming up in VGA modes. | * Changed the name of the routine I2CReadByte to DFPReadByte. This routine now uses DDC calls to read DFP EDID data. This change fixes the problem with detecting scaled and non-scaled DFPs and also scaled DFPs now fully supported. Also fixes problem with scaled DFP not coming up in VGA modes. | ||
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** In InitRegisters, always set DramInit0[30]=1 to force SDRAM. | ** In InitRegisters, always set DramInit0[30]=1 to force SDRAM. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 1.00 (03/24/2000)"> | <spoiler text="Version 1.00 (03/24/2000)"> | ||
* Changed the default DramInit timings for 143MHz MCLK. | * Changed the default DramInit timings for 143MHz MCLK. | ||
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** In OEMInitBIOS, added conditional compile code to disable the sync on the slaves chips only on 2-way and 4-way BIOSs. | ** In OEMInitBIOS, added conditional compile code to disable the sync on the slaves chips only on 2-way and 4-way BIOSs. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 1.05 (05/08/2000)"> | <spoiler text="Version 1.05 (05/08/2000)"> | ||
* Corrected VPD Checksum to allow for (ICT) Production BIOS programming. | * Corrected VPD Checksum to allow for (ICT) Production BIOS programming. | ||
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** Removed the build options for V5P847 and V5P874.ROM. | ** Removed the build options for V5P847 and V5P874.ROM. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 1.10 (06/16/2000)"> | <spoiler text="Version 1.10 (06/16/2000)"> | ||
* Modified the V5P896 build option to have vidProcCfg[29:28]=00 and all other BIOS builds have vidProcCfg[29:28] = 11. | * Modified the V5P896 build option to have vidProcCfg[29:28]=00 and all other BIOS builds have vidProcCfg[29:28] = 11. | ||
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** Change the memory clock for the V5P848 to 183 MHz. | ** Change the memory clock for the V5P848 to 183 MHz. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 1.15 (08/14/2000)"> | <spoiler text="Version 1.15 (08/14/2000)"> | ||
* Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec. | * Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec. | ||
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** Made the SGRAMMODE register setting coniditional compile for Napalm and Napalm2. Fixes problem with Napalm2 SGRAMMODE setting being used on Napalm. Fixes PRS#15511. | ** Made the SGRAMMODE register setting coniditional compile for Napalm and Napalm2. Fixes problem with Napalm2 SGRAMMODE setting being used on Napalm. Fixes PRS#15511. | ||
</spoiler> | </spoiler> | ||
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== Daytona (Voodoo4-2) == | == Daytona (Voodoo4-2) == | ||
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<spoiler text="Version 1.00 (07/21/2000)"> | <spoiler text="Version 1.00 (07/21/2000)"> | ||
* Initial version of the Napalm2 BIOS | * Initial version of the Napalm2 BIOS | ||
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** Changed DramInit0 to 0001EA9A9h. Made tRP = 2, row precharge = 3 clocks. | ** Changed DramInit0 to 0001EA9A9h. Made tRP = 2, row precharge = 3 clocks. | ||
</spoiler> | </spoiler> | ||
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<spoiler text="Version 1.03 (08/14/2000)"> | <spoiler text="Version 1.03 (08/14/2000)"> | ||
* Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec. | * Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec. | ||
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** Add strings to display total DDR or SDR memory. | ** Add strings to display total DDR or SDR memory. | ||
</spoiler> | </spoiler> | ||
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Latest revision as of 21:54, 14 December 2015
Napalm (Voodoo4 / Voodoo5)
