View source for RAM Timings

== Glossary ==

=== tCAS - Column Address Strobe Latency ===
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.


=== tRCD - Row Address to Column Address Delay ===
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.


=== tRP - Row Precharge Time ===
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.


=== tRAS - Row Active Time ===
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.


=== tRC - Row Cycle Time ===
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.


=== tRRD - Row Active to Row Active Delay ===
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.

== Timings ==

=== Banshee ===

{|class="wikitable"
!Voodoo Banshee
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
|Generic 1.00.03
|2
|2
|2
|3
|6
|1
|-
|Generic 1.00.10
|2
|1
|2
|5
|8
|1
|-
|Generic 1.00.10
|2
|2
|2
|5
|8
|2
|-
|Asus 1.00.01
|2
|2
|2
|3
|6
|1
|-
|Asus 1.00.03
|2
|2
|2
|5
|8
|2
|-
|Asus 1.00.04
|2
|2
|2
|3
|6
|1
|-
|Buffalo
|2
|2
|2
|4
|7
|2
|-
|Creative
|2
|2
|2
|5
|8
|2
|-
|Diamond 1.20 B4002 / 1.21 A4002
|2
|1
|2
|4
|7
|1
|-
|Diamond 1.20 B4803
|2
|2
|2
|3
|6
|1
|-
|Ensoniq
|2
|2
|2
|3
|6
|1
|-
|Elsa
|2
|2
|2
|3
|6
|1
|-
|EON
|2
|2
|2
|5
|8
|2
|-
|Gainward
|2
|1
|2
|5
|8
|2
|-
|GigaByte
|2
|2
|2
|3
|6
|1
|-
|innoVISION
|2
|1
|2
|5
|8
|1
|-
|IO-Data
|2
|2
|2
|5
|8
|1
|-
|Jace
|2
|2
|2
|3
|6
|1
|-
|Jetway
|2
|2
|2
|5
|8
|2
|-
|Leadtek
|2
|1
|2
|4
|7
|1
|-
|MetaBayte
|2
|1
|2
|5
|8
|1
|-
|miroMEDIA
|2
|1
|2
|5
|8
|1
|-
|PMC
|2
|2
|2
|3
|6
|1
|-
|Provideo
|2
|1
|2
|5
|8
|1
|-
|SigmaCom
|2
|2
|2
|5
|8
|2
|-
|Skywell 1.00.03
|2
|2
|2
|3
|6
|1
|-
|Skywell 1.00.10
|2
|2
|2
|5
|8
|2
|-
|STB
|2
|2
|2
|5
|8
|2
|-
|Typhoon
|2
|2
|2
|3
|6
|1
|-
|Viewtop 1.00.01
|2
|1
|2
|4
|7
|1
|-
|Viewtop 1.00.03
|2
|1
|2
|5
|8
|1
|-
|Quantum3D AArkvard
|2
|2
|2
|5
|8
|2
|-
|Quantum3D Raven 1.00.01
|2
|1
|2
|4
|7
|1
|-
|Quantum3D Raven 1.00.03
|2
|1
|2
|5
|8
|1
|-
|Quantum3D Raven 1.00.03-QA
|2
|2
|2
|5
|8
|1
|}

=== Avenger (Voodoo3) ===

{|class="wikitable"
!Voodoo3
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
|Voodoo3 1000
|2
|2
|2
|7
|10
|1
|-
|Voodoo3 2000
|2
|2
|2
|7
|10
|1
|-
|Voodoo3 3000
|2
|2
|2
|7
|10
|1
|-
|Voodoo3 3500TV
|2
|2
|2
|7
|10
|1
|-
|Falcon Northwest Voodoo3 3500
|2
|2
|3
|7
|10
|1
|}

=== Napalm (Voodoo4) ===

{|class="wikitable"
!Voodoo4
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
|Voodoo4 4500 AGP / PCI 1.10
|2
|2
|2
|6
|10
|1
|-
|Voodoo4 4500 AGP 1.11
|2
|2
|3
|6
|10
|1
|-
|Voodoo4 4500 AGP / PCI 1.15+
|2
|2
|2
|6
|10
|1
|-
|PowerColor EvilKing4 L-Shape
|2
|2
|2
|6
|10
|1
|-
|PowerColor EvilKing4 TV
|2
|2
|2
|6
|10
|1
|-
|Evate Voodoo4 4500
|2
|2
|2
|6
|10
|1
|-
|Voodoo4 4800 AGP 1.02+
|2
|2
|3
|6
|10
|1
|-
|Voodoo4 4800 AGP 1.15
|2
|2
|2
|6
|10
|1
|}

=== Napalm (Voodoo5) ===

{|class="wikitable"
!Voodoo5
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
|Voodoo5 5000 AGP
|x
|x
|x
|x
|x
|x
|-
|Voodoo5 5000 PCI
|2
|2
|3
|6
|10
|1
|-
|Voodoo5 5500 AGP 1.01 - 1.12
|2
|2
|3
|6
|10
|1
|-
|Voodoo5 5500 AGP 1.12+
|2
|2
|2
|6
|10
|1
|-
|Voodoo5 5500 PCI 1.00 / 1.11 / 1.15
|2
|2
|3
|6
|10
|1
|-
|Voodoo5 5500 PCI 1.08 / 1.16+
|2
|2
|2
|6
|10
|1
|-
|Voodoo5 6000 AGP 0.27 - 0.32
|2
|1
|2
|4
|7
|1
|-
|Voodoo5 6000 AGP 1.11
|2
|2
|3
|6
|10
|1
|-
|Voodoo5 6000 AGP 1.16+
|2
|2
|3
|7
|11
|1
|}

=== Daytona (Voodoo4-2) ===

{|class="wikitable"
!Voodoo4-2
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
|Voodoo4-2 4000 AGP
|x
|x
|x
|x
|x
|x
|-
|Voodoo4-2 4200 AGP
|x
|x
|x
|13
|x
|x
|-
|Voodoo4-2 4200 PCI
|3
|2
|2
|6
|10
|1
|-
|Voodoo4-2 4800
|x
|x
|x
|x
|x
|x
|}