Difference between revisions of "RAM Timings"
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=== tCAS - Column Address Strobe Latency === | === tCAS - Column Address Strobe Latency === | ||
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs. | The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs. | ||
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=== tRRD - Row Active to Row Active Delay === | === tRRD - Row Active to Row Active Delay === | ||
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD. | The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD. | ||
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| + | == Timings == | ||
=== Voodoo Banshee === | === Voodoo Banshee === | ||
Revision as of 14:52, 7 June 2015
What
tCAS - Column Address Strobe Latency
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.
tRCD - Row Address to Column Address Delay
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.
tRP - Row Precharge Time
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.
tRAS - Row Active Time
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.
tRC - Row Cycle Time
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
tRRD - Row Active to Row Active Delay
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.
Timings
Voodoo Banshee
| Voodoo Banshee | tCAS | tRCD | tRP | tRAS | tRC | tRRD |
|---|---|---|---|---|---|---|
| Generic 1.00.03 | 2 | 2 | 2 | 3 | 6 | 1 |
