RAM Timings - Revision history

Administrator at 18:20, 22 September 2015

2015-09-22T18:20:06Z

Administrator at 20:02, 7 June 2015

2015-06-07T20:02:06Z

Administrator at 13:41, 7 June 2015

2015-06-07T13:41:26Z

Administrator at 13:40, 7 June 2015

2015-06-07T13:40:31Z

Administrator at 13:36, 7 June 2015

2015-06-07T13:36:17Z

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Administrator at 13:24, 7 June 2015

2015-06-07T13:24:48Z

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Administrator at 12:52, 7 June 2015

2015-06-07T12:52:06Z

Administrator: Created page with "=== tCAS - Column Address Strobe Latency === The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available o..."

2015-06-07T12:48:00Z

Created page with "=== tCAS - Column Address Strobe Latency === The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available o..."

New page

=== tCAS - Column Address Strobe Latency ===
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.

=== tRCD - Row Address to Column Address Delay ===
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.

=== tRP - Row Precharge Time ===
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.

=== tRAS - Row Active Time ===
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.

=== tRC - Row Cycle Time ===
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

=== tRRD - Row Active to Row Active Delay ===
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.

=== Voodoo Banshee ===

{| class="wikitable"
!Voodoo Banshee
!tCAS
!tRCD
!tRP
!tRAS
!tRC
!tRRD
|-
| Generic 1.00.03
|2
|2
|2
|3
|6
|1

← Older revision		Revision as of 18:20, 22 September 2015
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−	== ~~What~~ ==	+	== Glossary ==

	=== tCAS - Column Address Strobe Latency ===		=== tCAS - Column Address Strobe Latency ===

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 {|class="wikitable"
-! Voodoo Banshee
+!Voodoo Banshee
 !tCAS
 !tRCD

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 == Timings ==
-=== Voodoo Banshee ===
+=== Banshee ===
 {|class="wikitable"

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 === Avenger (Voodoo3) ===
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 |1
 === Napalm (Voodoo4) ===
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 |1
 === Napalm (Voodoo5) ===
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 === Daytona (Voodoo4-2) ===
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 |x
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 === tCAS - Column Address Strobe Latency ===
 The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.
@@ Line 21: / Line 24: @@
 === tRRD - Row Active to Row Active Delay ===
 The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.
 === Voodoo Banshee ===