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        <title>3dfx-BIOS</title>
        <description></description>
        <link>http://3dfxbios.cl-rahden.de/</link>
        <lastBuildDate>Sun, 20 May 2012 22:43:48 +0200</lastBuildDate>
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            <title>3dfx-BIOS</title>
            <link>http://3dfxbios.cl-rahden.de/</link>
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        <item>
            <title>3dfx BIOS-Datenbank</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=hauptseite&amp;rev=1333401082</link>
            <description>
&lt;h1 class=&quot;sectionedit1&quot;&gt;&lt;a name=&quot;dfx_bios-datenbank&quot; id=&quot;dfx_bios-datenbank&quot;&gt;3dfx BIOS-Datenbank&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;p&gt;
Nach ungefähr 5 Jahren des Sammelns habe ich mich entschlossen eine BIOS-Datenbank zu erstellen. Sinn und Zweck dieser ist es meine Sammlung allen 3dfx-Verrückten zur Verfügung zu stellen. &lt;br/&gt;

&lt;br/&gt;

Das soll nun jedoch nicht heißen, dass dies der finale Stand ist. Auch wenn es schwieriger wird neue BIOS-Dateien zu bekommen, hoffe ich auf eure Hilfe. Jeder der sich hier nach neuen BIOS-Dateien umschaut, hat sich schon mit dem Thema BIOS befasst und sollte, bevor er ein neues BIOS auf die Karte flasht, schauen, ob das Original-BIOS der Karte schon in dieser Datenbank gelistet ist. Ist dies nicht der Fall, ist die Rubrik &lt;a href=&quot;http://3dfxbios.cl-rahden.de/doku.php?id=wiki:tools:unterstuetzung&quot; class=&quot;wikilink1&quot; target=&quot;_self&quot; title=&quot;wiki:tools:unterstuetzung&quot;&gt;Unterstützung&lt;/a&gt; aufzusuchen. Dort wird erklärt, wie ihr mich hier unterstützen könnt.&lt;br/&gt;

&lt;br/&gt;

Es wird sich noch einiges an dieser Homepage verändern. Vor allem wird darüber nachgedacht, diese komplett auf Englisch zu machen, damit sie international nutzbar ist.&lt;br/&gt;

Am besten ihr abnonniert den &lt;a href=&quot;http://www.cl-rahden.de/3dfxbios/feed.php&quot; class=&quot;urlextern&quot; target=&quot;_blank&quot; title=&quot;http://www.cl-rahden.de/3dfxbios/feed.php&quot;  rel=&quot;nofollow&quot;&gt;News-Feed&lt;/a&gt;, damit ihr immer auf dem laufenden bleibt.
&lt;br/&gt;

&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;aktuelle_anzahl&quot; id=&quot;aktuelle_anzahl&quot;&gt;Aktuelle Anzahl&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOS-Dateien: 222&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Flashkits: 15&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Tools: 13&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;was_ist_noch_zu_tun&quot; id=&quot;was_ist_noch_zu_tun&quot;&gt;Was ist noch zu tun?&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Einfügen von MD5-Hashcodes zur Verifizierung&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Umstellung auf Englisch&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Wechsel der Wiki-Distribution&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;was_ist_neu&quot; id=&quot;was_ist_neu&quot;&gt;Was ist neu?&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 02.04.2012: Update (3dfx Flash Tools &amp;amp; Release-Notes)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 01.04.2012: Release-Notes für Napalm-/Daytona-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 31.03.2012: Update (BIOS, Flashkits, Tools)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 13.10.2011: Update (Voodoo5 6000, Diverses)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 26.08.2011: Update (VoodooMAC, Diverses)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 12.11.2009: Übersicht aller 3dfx-Karten ab Voodoo3&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 14.10.2009: Veröffentlichung&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10.10.2009: Start des Projektes &lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;br/&gt;

&lt;br/&gt;

&lt;br/&gt;

Ohne Hilfe wäre eine solche Datenbank nicht zu realisieren. Besonders die vielen Prototypen-BIOS&amp;#039; wären ohne die Hilfe der echten Sammler nicht auffindbar gewesen. Aus diesem Grund möchte ich mich bei diesen namentlich bedanken.&lt;br/&gt;

&lt;br/&gt;

Mein Dank geht an: &lt;strong&gt;exxe, Eye-Q, FalconFly, gdonovan, j-dogg, logicalmadness, m14radu, Nightbird, Obi-Wan, osckhar, RazrX &amp;amp; Rolo01&lt;/strong&gt; (in alphabetischer Reihenfolge)&lt;br/&gt;

&lt;/p&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;br/&gt;

&lt;br/&gt;

&lt;br/&gt;

Copyright 2009-2012

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&lt;/p&gt;

&lt;/div&gt;
</description>
            <author>chosen_one</author>
            <pubDate>Mon, 02 Apr 2012 23:11:22 +0200</pubDate>
        </item>
        <item>
            <title>Tools</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=wiki:tools:tools&amp;rev=1333400833</link>
            <description>
&lt;h1 class=&quot;sectionedit2&quot;&gt;&lt;a name=&quot;tools&quot; id=&quot;tools&quot;&gt;Tools&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;p&gt;
Die hier hinterlegten Programme werden benötigt, um BIOS-Dateien zu betrachten, sichern und flashen. &lt;br/&gt;

&lt;br/&gt;

&lt;/p&gt;

&lt;p&gt;
&lt;strong&gt;Die Nutzung der hier aufgeführten Programme geschieht auf eigene Gefahr. &lt;br/&gt;

Ich übernehme keine Haftung für eventuelle Schäden an Hard- bzw. Software!&lt;/strong&gt;&lt;br/&gt;

&lt;br/&gt;

&lt;strong&gt;Die Urheberrechte liegen beim jeweiligen Autor.&lt;/strong&gt;&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;
&lt;!-- EDIT2 SECTION &quot;Tools&quot; [1-350] --&gt;
&lt;h2 class=&quot;sectionedit3&quot;&gt;&lt;a name=&quot;windows&quot; id=&quot;windows&quot;&gt;Windows&lt;/a&gt;&lt;/h2&gt;
&lt;div class=&quot;level2&quot;&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;dfx_bios_editor_10&quot; id=&quot;dfx_bios_editor_10&quot;&gt;3dfx BIOS Editor 1.0&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_bios_editor_1.0.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_bios_editor_1.0.7z&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Dieser BIOS-Editor ist ein Standard-Editor zum Betrachten einer BIOS-Datei. Dieser Editor wird jedoch nur der Vollständigkeit halber aufgeführt.
&lt;/p&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;dfx_flash&quot; id=&quot;dfx_flash&quot;&gt;3dfx Flash&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;3dfx Flash Tools&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_1.04.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_1.04.7z&quot;&gt;Download: 3dfx Flash 1.04&lt;/a&gt; (Achtung: Nur für Voodoo Banshee!)&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_2.12.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_2.12.7z&quot;&gt;Download: 3dfx Flash 2.12&lt;/a&gt;&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_2.13.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_2.13.7z&quot;&gt;Download: 3dfx Flash 2.13&lt;/a&gt;&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_2.14.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_2.14.7z&quot;&gt;Download: 3dfx Flash 2.14&lt;/a&gt;&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_2.17.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_2.17.7z&quot;&gt;Download: 3dfx Flash 2.17&lt;/a&gt;&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Release-Notes&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.00 - 2.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.00&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/10/99 - FLASH Version 2.00&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; This flash version will flash either a 32K or 64K binary image. It will also save off the previos BIOS according to its size. The Atmel 29LV512, 49BV512 and SST27LE512 are now supported.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed version number.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added dwOldROMSaveSize and dwNewBinFileSize for ROM and Bin file sizes.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the file size checking to allow the variance between 64K and 32K.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the ID&amp;#039;s for the new EEPROMs.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the hard coded values of above.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.01&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/24/99 - FLASH Version 2.01&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH now supports both Banshee and Avenger. This fixes PRS#4394.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with 32K ROM subvendor and subsystem ID not being shadowed onto the upper 64K. This fixes PRS#4434.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Enabled code which shadows the PCI subsystem and subvendor ID to the upper 64K of ROM when flashing a 32K BIOS. Fixes PRS#4394.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the strings szCopyright and szNoBoard to have no reference to Voodoo3. This is so that the flash will work on both Banshee and Voodoo3. Fixes PRS#4434.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitBoard, removed the check for Voodoo3 2000 and added a check for Banshee.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Main, added a check for the ATMEL 29LV512 parts.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.02&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/25/99 - FLASH Version 2.02&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with not being able to flash a 32K BIOS on a board strapped for 32K. Fixes PRS#4617.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In WriteROMFromFile, added the ROM size strapping, MiscInit0[24], to determine if the board is strapped for 32K or 64K before deciding if the PCI subvendor and subsystem ID needs to be shadowed to the upper 64K of the ROM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.03&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 3/04/99 - FLASH Version 2.03&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for 40K BIOSs. This must be used with all 40K BIOSs!&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In WriteROMFromFile, added code to handle 40K ROMs in a 64K ROM file binary.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.04&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 3/05/99 - FLASH Version 2.04&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed problem with not being able to create a SAVE.ROM image when the SAVE.ROM ROM size was 40K. Fixes PRS#4852.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; The the main routine, modified the check for a 64K ROM to check for anything above 32K, and will then assume a 64K ROM binary.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.05&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 3/18/99 - FLASH Version 2.05&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In WriteROMFromFile, added code to handle programming a 32K ROM which is in a 64K Binary.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.06&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/1/99 - FLASH Version 2.06&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Makefile&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added PCIINFO.CPP.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Board descriptor info and bumped version to 2.06.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for multiple boards in system.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; USER.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added ContinueYN function.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for multiple boards and board info.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; PCIINFO.CPP &amp;amp; VIDIN.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; New files.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.07&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/5/99 - FLASH Version 2.07&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; PCIINFO.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed errors in the type casting of variables in the routines _pciCreateConfigSpaceMapping and the PCIEnumerate.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed some of the „3Dfx“ strings to say „3dfx“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.08&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/20/99 - FLASH Version 2.08&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added new SSIDs for the new Voodoo3 and Velocity series products.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/22/99 - FLASH Version 2.09&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for flashing Napalm and Rampage.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Clean up some of the compiler warning messages in PCIINFO.CPP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created seperate chip strings, ChipSpeedVer tables, and ChipBuildInfo tables for V3, Napalm, and Rampage.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Napalm and Rampage into the Device name table.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made wDeviceId a global variable.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created #define ChipId for Napalm and Rampage.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created seperate ChipSpeedVer and ChipBuildInfo table size defines for V3, Napalm, and Rampage.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Napalm and Rampage intot he ChipSpeedtype enumerated table.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „V3_“ variables to „CHIP_“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the ChipSpeedVer strucuture to include BusType.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the SelectBoard routine to use the TdfxDeviceName table to get the board name.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the ValidateNewRom to handle searching Napalam and Rampage. The changes were made in a way so that adding support for a new chip can easily be made.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; PCIINFO.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Commented out some of the PCIINFO variables to remove the warning messages generated by the compilier.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In BeginROM, added code to program MiscInit[2] to enable ROM Writes on Rampage only. Napalam and V3 programs MiscInit[4] to enable ROM writes.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.10 - 2.17&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.10&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/15/00 - FLASH Version 2.10&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed error with not being able to detect Voodoo4 and Voodoo5 cards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm PCI device ID from 0x07 to 0x09.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated Napalm board configuration tables.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm device ID from 0x07 to 0x09.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the ChipSpeedType struture for the all the Napalm board types.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created externs for sVoodoo4 and sVoodoo5 BIOS string names.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug in sNapalmBuilds and sRampageBuilds extern defination.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the strings sVoodoo4 and sVoodoo5.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the structures sNapalmSpeedVer and sNapalmBuilds.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the version number to 2.10.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In ValidateNewROM, added check for Voodoo4 and Voodoo5. Also modified scheme to check for SDRAM and SGRAM Napalm BIOS. Will now read the board configuration DWORD instead of searching for the “-SD“ or “-SG“ string.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.11&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/15/00 - FLASH Version 2.11&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with not being able to flash PCI cards on a Camino motherboard. Camino systems have the PCI bus on bus 2 not bus 0.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VIDIN.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the MAX_PCI_DEVICES to scan 00h to 0Fh buses for 3dfx cards.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.12&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/2/00 - FLASH Version 2.12&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with trying to FLASH bios while in a full screen DOS session and after running Windows. Fixes PRS#12546.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In BeginRom, save the original state of MiscInit0 and cleared MiscInit0[30]=0 begin flash the ROM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In EndRom, restored the original state of MiscInit0.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitBoard, initilized the variable lpLinMiscInit0 with the current miscInit0 value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the variables dwOrgMiscInit0 and lpLimMiscInit0.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the externs dwOrgMiscInit0 and lpLinMiscInit0.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.13&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 3/7/00 - FLASH Version 2.13&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Combined the FLASH and USERFLASH code base into one source tree.&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; To compile FLASH,&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Type „nmake clean“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Type „nmake“. Resulting file is FLASH.EXE.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; To compile USERFLASH, &lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Type „nmake -fuserflsh.mak clean“.  &lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Type „nmake -fuserflsh.mak“. Resulting file is USERFLSH.EXE.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; UserFlash coded is conditionally compiled.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for the SST 39VF512 flash part.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for the Velocity and Voodoo3 1000 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; USAGE.TXT UserFlash Usage.txt&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; UserFlash usage documents.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; USERFLSH.MAK&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Makefile for creating USERFLSH.EXE.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added #defines for the offsets to the OEMConfig table.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added #defines for the size and register offsets to the Voodoo3, Napalm and Rampage OemConfig tables.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added #define for the SST_35VF512 device ID.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Increased the number for V3 boards from 59 to 74.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the ChipSpeedType structure for the Velocity 100 and 200 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added defines for UserFlash routines and variables.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the constant NUM_REGS into a variable.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the variable sVd3Velocity to check for the „Velocity“ string in the BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the structure ChipSpeedVer, added support for the Velocity 100/200 and Voodoo3 1000 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the structure sV3Builds, added the board configurations for the Velocity 100/200 and Voodoo3 1000 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added UserFlash variables byVPDBuffer abd byRegisterOffset.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the „Napalm“ string to „VSA 100“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Conditonally compilied two seperate set of copyright and usage messages for FLASH and USERFLSH.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added variables and boolean flags for the USERFLASH command line override options.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the USERFLASH structure sOEMCfgREgInfo to default to use the V3 OEMConfig strurcture.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the USERFLASH code to properly generate the correct escape codes when printing error messages.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the main routine, added USERFLASH code to initilize all the command line flags to false. Also parsed the command line parameters and set the appropiate flags.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the main routine, added a check for the SST 39VF512 flash part.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the main routine, added the USERFLASH code to compare version numbers. If the current BIOS version is newer than the BIOS to be flashed, a warning message is printed. Also added USERFLASH code to not preserve the original OEMConfig register settings and use the new settings in the binary file about to be flashed.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the ValidateNewRom routine, added a check for the Velocity BIOS. Also added UserFlash code to skip the check of the SSID and board configuration.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine SaveRom, added UserFlash code to save the VPD structure.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine WriteROMRestore, modified the loop to always assume a 64K BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine WriteROMFromFile, added UserFlash code to restore settings depending on the command line flag settings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine ROMVerifyWrite, added support for the SST 35VF512 flash part.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the following UserFlash routines:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; IsVPDAvailable&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Check if the old ROM had a VPD to update&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; SaveOffOldRegs&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Save the configuration table for the register settings of the old BIOS. To be maintained when the new BIOS is flashed.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; GetNewRegsSettingPtr&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Return the WORD pointer for the Register settings table within the new BIOS file. &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; CopyInOldRegs&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Copy the Original Register settings from the old BIOS into the new BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; NewFileVPDAvailable&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Check the file intended to be flashed to see if the VPD structure is there&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; CheckLaterVersion&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; Will compare the versions of the ROM and the new file to see which is later&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.14&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/4/00 - FLASH Version 2.14&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for the Napalm V5-5800 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the number of Napalm board options, NUM_NAPALM_BUILDS, to 16 and the number of Napalm speed options, NUM_NAPALM_SPEED, to 5.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the ChipSpeedType structure to include Napalm_5800.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the sChipSpeedVer variable to support for to 10 speed types.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the Napalm 5800 to the sNapalmSpeedVer and sNapalmBuilds structures.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.15&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/17/00 - FLASH Version 2.15&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for the Napalm2.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In ValidateNewRom, expanded the Napalm chip ID check to also include Napalm2.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added “#define ChipIdNapalm2 0x0B“ for the Napalm2 chip ID.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated NUM_TDFX_CHIPS to 6.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.16&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/12/00 - FLASH Version 2.16&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with last entry in the structures SpeedVer and Builds wer never read.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with Napalm BIOS builds not properly being found when multiple subvendor IDs were used for a set of BIOS builds.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Daytona UserFlash code to perserve the Strapping Option DWORDS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Napalm support for the Napalm 4400 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Daytona support for the Daytona 4200 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In ValidateNewROM, fixed bug with size of SpeedVer and Builds structures not properly being read. In ValidateNewRom, expanded the check for the SubVendor ID to also check the bus type and BIOS speed.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added #defines for the offsets to the strapping option data.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Napalm support for the Napalm 4400 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Daytona support for the Daytona 4200 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Expanded the ChipSpeedVer and Napalm Build structures to include Napalm 4400.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the Napalm build for the V5P901 Voodoo5 5800.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; ROM.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In BeginROM, expand the check for Napalm to also include a check for Napalm2.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Expanded the WriteROMFromFile routine to also preserve the strapping options DWORDS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 2.17&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/12/00 - FLASH Version 2.17&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Daytona support for the Daytona 4000 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.CPP&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Expanded the ChipSpeedVer and Napalm Build structures to include the Daytona 4000.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FLASH.H&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added Daytona support for the Daytona 4000 boards.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Source Codes&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:3dfx_flash_2.17_source.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:3dfx_flash_2.17_source.7z&quot;&gt;Download: 3dfx Flash 2.17 (Source Code)&lt;/a&gt;&lt;br/&gt;
&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;
&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;dumpbios&quot; id=&quot;dumpbios&quot;&gt;DumpBIOS&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:dump_bios.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:dump_bios.7z&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Mit Hilfe dieses Tools ist es möglich, das aktuell verwendete BIOS zu sichern. Hierzu ist das Archiv zu entpacken und auszuführen. Das BIOS wird dann als BIOS.BIN im Ordner hinterlegt.&lt;br/&gt;

Das Tool kann unter DOS oder Windows verwendet werden.
&lt;/p&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;tdfx_bios-editor_162&quot; id=&quot;tdfx_bios-editor_162&quot;&gt;tdfx BIOS-Editor 1.62&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:tdfx_bioseditor_1.62.7z&quot; class=&quot;media mediafile mf_7z&quot; title=&quot;upload:tools:tdfx_bioseditor_1.62.7z&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Der tdfx BIOS-Editor ist der BIOS-Editor, wenn es darum geht 3dfx-BIOS-Dateien zu sichten oder Veränderungen vorzunehmen.&lt;br/&gt;

Eine genaue Beschreibung der einzelnen Funktionen ist dem Readme-&lt;acronym title=&quot;Portable Document Format&quot;&gt;PDF&lt;/acronym&gt; im Archiv zu entnehmen.
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;
&lt;!-- EDIT3 SECTION &quot;Windows&quot; [351-14900] --&gt;
&lt;h2 class=&quot;sectionedit4&quot;&gt;&lt;a name=&quot;macos&quot; id=&quot;macos&quot;&gt;MacOS&lt;/a&gt;&lt;/h2&gt;
&lt;div class=&quot;level2&quot;&gt;

&lt;p&gt;
Auf Grund eines fehlendes Testsystem mit Macintosh kann ich die genaue Funktionsweise der unten genannten Programme leider nicht beschreiben.&lt;br/&gt;

Für Informationen/Screenshots der unten aufgeführten Programme wäre ich sehr dankbar!
&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo3_flasher&quot; id=&quot;voodoo3_flasher&quot;&gt;Voodoo3 Flasher&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:voodoo_mac_3_flasher.hqx&quot; class=&quot;media mediafile mf_hqx&quot; title=&quot;upload:tools:voodoo_mac_3_flasher.hqx&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Flashprogramm für die 3dfx Voodoo3.
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo3_flasher_new&quot; id=&quot;voodoo3_flasher_new&quot;&gt;Voodoo3 Flasher *NEW*&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:voodoo_mac_3_flasher_new.sit&quot; class=&quot;media mediafile mf_sit&quot; title=&quot;upload:tools:voodoo_mac_3_flasher_new.sit&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Neuere Version des Flashprogramms für 3dfx Voodoo3.&lt;br/&gt;

Änderungen zur älteren Version nicht bekannt.
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo3_rom-clocker_11b1&quot; id=&quot;voodoo3_rom-clocker_11b1&quot;&gt;Voodoo3 ROM-Clocker 1.1b1&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:voodoo_mac_3_rom-clocker_1.1b1.sit&quot; class=&quot;media mediafile mf_sit&quot; title=&quot;upload:tools:voodoo_mac_3_rom-clocker_1.1b1.sit&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Mit diesem Tool können die Taktraten der 3dfx Voodoo3 für den Mac geändert werden.
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoomac_4_5_flasher&quot; id=&quot;voodoomac_4_5_flasher&quot;&gt;VoodooMAC 4/5 Flasher&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:voodoo_mac_4-5_flasher.sit&quot; class=&quot;media mediafile mf_sit&quot; title=&quot;upload:tools:voodoo_mac_4-5_flasher.sit&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Flashprogramm für die 3dfx VoodooMAC 4/5.
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoomac_4_5_flasher_101&quot; id=&quot;voodoomac_4_5_flasher_101&quot;&gt;VoodooMAC 4/5 Flasher 1.01&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:tools:voodoo_mac_4-5_flasher_1.01.sea&quot; class=&quot;media mediafile mf_sea&quot; title=&quot;upload:tools:voodoo_mac_4-5_flasher_1.01.sea&quot;&gt;Download&lt;/a&gt; &lt;br/&gt;

Flashprogramm für die 3dfx VoodooMAC 4/5. Auf Grund der Größe der Datei können hier die BIOS-Dateien schon integriert sein.&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;
&lt;!-- EDIT4 SECTION &quot;MacOS&quot; [14901-] --&gt;</description>
            <author>chosen_one</author>
        <category>wiki:tools</category>
            <pubDate>Mon, 02 Apr 2012 23:07:13 +0200</pubDate>
        </item>
        <item>
            <title>Quantum3D</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=wiki:quantum3d:quantum3d&amp;rev=1333313976</link>
            <description>
&lt;h1 class=&quot;sectionedit5&quot;&gt;&lt;a name=&quot;quantum3d&quot; id=&quot;quantum3d&quot;&gt;Quantum3D&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_logo.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_logo.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_logo.jpg&quot; class=&quot;media&quot; title=&quot;Copyright: Quantum3D Inc.&quot; alt=&quot;Copyright: Quantum3D Inc.&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;p&gt;
&lt;strong&gt;Die Nutzung der hier aufgeführten BIOS-Dateien geschieht auf eigene Gefahr. &lt;br/&gt;

Ich übernehme keine Haftung für eventuelle Schäden an Hard- bzw. Software!&lt;/strong&gt;
&lt;/p&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;mgv&quot; id=&quot;mgv&quot;&gt;MGV&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_rush.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_rush.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_rush.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.dodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.dodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:mgv:mgv_4.30.00.28_pal.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:mgv:mgv_4.30.00.28_pal.rom&quot;&gt;Quantum3D MGV 4.30.00.28&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; PAL&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; TV-Out&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 05.01.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:mgv:mgv_4.30.00.28_ntsc.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:mgv:mgv_4.30.00.28_ntsc.rom&quot;&gt;Quantum3D MGV 4.30.00.28&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; NTSC&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; TV-Out&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 05.01.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;hr /&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;aardvard&quot; id=&quot;aardvard&quot;&gt;AArdvard&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;pci&quot; id=&quot;pci&quot;&gt;PCI&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_aardvark_pci.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_aardvark_pci.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_aardvark_pci.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.dodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.dodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sg-ram&quot; id=&quot;sg-ram&quot;&gt;SG-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:aardvark:pci:aardvark_pci_sg-ram_1.00.10.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:aardvark:pci:aardvark_pci_sg-ram_1.00.10.rom&quot;&gt;Quantum3D AArdvark PCI SG-RAM 1.00.10&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 18.08.1999&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;hr /&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;raven&quot; id=&quot;raven&quot;&gt;Raven&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;agp&quot; id=&quot;agp&quot;&gt;AGP&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_raven_agp.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_raven_agp.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_raven_agp.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.dodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.dodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sd-ram&quot; id=&quot;sd-ram&quot;&gt;SD-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:raven:agp:raven_agp_sd-ram_1.00.03.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:raven:agp:raven_agp_sd-ram_1.00.03.rom&quot;&gt;Quantum3D Raven AGP SD-RAM 1.00.03&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10.10.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:raven:agp:raven_agp_sd-ram_1.00.03-qa.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:raven:agp:raven_agp_sd-ram_1.00.03-qa.rom&quot;&gt;Quantum3D Raven AGP SD-RAM 1.00.03 QA&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; QA-Zusatz (Quality Assurance) weist auf ein intern verwendetes BIOS hin&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 19.11.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;pci1&quot; id=&quot;pci1&quot;&gt;PCI&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_raven_pci.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_raven_pci.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_raven_pci.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.dodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.dodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sd-ram1&quot; id=&quot;sd-ram1&quot;&gt;SD-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:raven:pci:raven_pci_sd-ram_1.00.01.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:raven:pci:raven_pci_sd-ram_1.00.01.rom&quot;&gt;Quantum3D Raven PCI SD-RAM 1.00.01&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 24.08.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:raven:pci:raven_pci_sd-ram_1.00.03.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:raven:pci:raven_pci_sd-ram_1.00.03.rom&quot;&gt;Quantum3D Raven PCI SD-RAM 1.00.03&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10.10.1998&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;hr /&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;ventana3&quot; id=&quot;ventana3&quot;&gt;Ventana3&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;pci2&quot; id=&quot;pci2&quot;&gt;PCI&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Aquantum3d%3Aquantum3d&amp;amp;media=upload:bilder:q3d_3500.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:q3d_3500.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:q3d_3500.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.dodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.dodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sg-ram1&quot; id=&quot;sg-ram1&quot;&gt;SG-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:ventana3:pci:sg-ram:ventana3-c_pci_sg-ram_2.15.06.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:ventana3:pci:sg-ram:ventana3-c_pci_sg-ram_2.15.06.rom&quot;&gt;Quantum3D Ventana3-C PCI SG-RAM 2.15.06&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 28.10.1999&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:quantum3d:ventana3:pci:sg-ram:ventana3_3500_pci_sg-ram_2.15.06_181mhz.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:quantum3d:ventana3:pci:sg-ram:ventana3_3500_pci_sg-ram_2.15.06_181mhz.rom&quot;&gt;Quantum3D Ventana3 3500 PCI SG-RAM 2.15.06&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 181/181 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.10.1999&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;/div&gt;
</description>
            <author>chosen_one</author>
        <category>wiki:quantum3d</category>
            <pubDate>Sun, 01 Apr 2012 22:59:36 +0200</pubDate>
        </item>
        <item>
            <title>Statistik</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=wiki:statistik&amp;rev=1333311318</link>
            <description>
&lt;h1 class=&quot;sectionedit6&quot;&gt;&lt;a name=&quot;statistik&quot; id=&quot;statistik&quot;&gt;Statistik&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;p&gt;
Hier seht ihr den leider sehr bescheidenen Fortschritt…
&lt;/p&gt;
&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt; 2012&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_5_2012.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_4_2012.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_2_2012.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_1_2012.png&quot; /&gt;&lt;/div&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt; 2011&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_12_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_11_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_10_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_9_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_8_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_7_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_6_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_5_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_4_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_3_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_2_2011.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_1_2011.png&quot; /&gt;&lt;/div&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt; 2010&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_12_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_11_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_10_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_9_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_8_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_7_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_6_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_5_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_4_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_3_2010.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_2_2010.png&quot; /&gt;&lt;/div&gt;
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&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt; 2009&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_12_2009.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_11_2009.png&quot; /&gt;&lt;/div&gt;
&lt;div class=&quot;info_hof&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=wikistatistics:histocontrib_10_2009.png&quot; /&gt;&lt;/div&gt;
&lt;/div&gt;&lt;/div&gt;
&lt;/div&gt;
</description>
            <author>chosen_one</author>
        <category>wiki</category>
            <pubDate>Sun, 01 Apr 2012 22:15:18 +0200</pubDate>
        </item>
        <item>
            <title>BIOS Release-Notes</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=wiki:misc:release-notes&amp;rev=1333310490</link>
            <description>
&lt;h1 class=&quot;sectionedit7&quot;&gt;&lt;a name=&quot;bios_release-notes&quot; id=&quot;bios_release-notes&quot;&gt;BIOS Release-Notes&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;napalm_voodoo4_voodoo5&quot; id=&quot;napalm_voodoo4_voodoo5&quot;&gt;Napalm (Voodoo4 / Voodoo5)&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.01 - 0.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.01&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/30/99 - Ver. 0.01&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Initial Version of Napalm BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Based on the Avenger BIOS version 2.11.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.02&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/4/99 - Ver. 0.02&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added 1280&amp;times;1024 panel timings. By default, BIOS assumes a 1024&amp;times;768 panel where CR1D[6]=0. To tell the BIOS a 1280&amp;times;1024 panel is attached, CR1D[6]=1.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with some ROM binaries not booting. Fixes PRS#5619&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the routines GetSubdeviceID and GetSubvendorID to get the offset to the tblPCIInfo table from read C000:0018 instead of using the tblPCIInfo label.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the Panel routine to check if a 1280&amp;times;1024 panel is attached to determine which set of panel timings to load.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine GetPanelSize, to return the size of panel currently attached.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the field FL_PANEL1280 for determing when a 1280&amp;times;1024 panel is attached.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added 1280&amp;times;1024 panel timings into tblExtRegisters and the XLCD_Patch_Table table.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.03&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/5/99 - Ver. 0.03 &lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Create one universal ROM for both SDRAM and SGRAM. Added support for 32Meg and 64Meg of video memory.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMSignOn, modified the sign on message to also print if SDRAM or SGRAM was detected.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Replaced the SDRAM_BIOS compile option with a call to the routine CheckIfSGRAM in the following routines:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; InitRegisters&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMGetMemSize&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified OEMSignOn to handle 32Meg and 64Meg sign on message.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified OEMGetMemSize to handle return 32Meg and 64Meg of memory installed.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed all the conditional compile options for SDRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the “-SD“ and “-SG“ from the STR_OEMVERSION string.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the field FLD_SDRAMBOARD.  This is tested against DramInit1 to determine if SDRAM or SGRAM memory.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the strings szSDRAM_Memory and szSGRAM_Memory.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the strings sz32768K and sz65536K.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.04&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/11/99 - Ver. 0.04&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the 32K ROM only, moved all the routines that are executed only during POST into the upper 32K of the ROM.  These routines will be discarded after VGA POST s executed.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOSEND.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; For the 32K ROM only, added 1500 bytes of padding, db 1500 dup (FFh), to push the BIOS POST past the 32K barrier.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; For the 32K ROM only, added code to patch the ROM size to 32K at C000:0002 and the PCI Info block. This patch isn&amp;#039;t executed if the BIOS detects that the ROM size at C000;0002 is set to 64K.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; This is to work around an issue on the Compaq 5240 machine.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Set the 32K ROM size to report a 40K ROM. This is later patched to report 32K by the routine InitBIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAKEFILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the new file OEMPOST.ASM into the build process. Modified the link process to link INIT.obj and OEMPOST.obj after BIOSEND.obj.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the compile option for tblExtRegisters table.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the TV parameters for the tblExtRegisters table for a non-TV BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; For the 32K BIOS only, modified the PCI Info block to report a 40K BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; This is later patched to report 32K by the routine InitBIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved all VGA	POST routines into this files. These POST routines are:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMInitBIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMInitWakeUp&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMNoMonitor&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMSignOn&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; InitIOBase&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; InitRegisters&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the EXTREGS structure, added a LCD and TV compile option for xrTVOutIdx.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved routines which are only needed during POST to OEMPOST.ASM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Merge the routines GetSubdeviceID and GetSubvendorID into GetSSID.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.05&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/17/99 - Ver. 0.05&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with Protect mode Set Display Start Address routine, function 07h, not properly detecting the start of Vertical start. This fixes problem with SciTeck Display Doctor not displaying the correct frame rate during the page flipping test.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the VBE protected mode function, Set Display Start Address, to also look for active display when checking for VSYNC. This will guarantee you will find the start of VSYNC.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.06&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/21/99 - Ver. 0.06&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated all the LCD centering parameters so that they are centered on the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug in GetExtRegsEntry routine to properly load parameters from the EXTREGS table for 200, 350, and 400 scanline text mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified GetExtRegsEntry routine to properly load parameters from the EXTREGS table for 200, 350, and 400 scanline text mode.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In tblModeDescriptions, changed the internal mode number for modes 00,01,02,03, to 00, 01, 02, and 03h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In tblExtRegisters, adjusted all the 1024&amp;times;768 panel CR04, CR05, CR10, and CR11 settings to center the image on the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.07&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/28/99 - Ver. 0.07&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the VESA DDC EDID read routine to read DDC from the panel when active.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added code to check if a panel is detected during POST.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added code to check if we want to force a SVideo/Composite or autodetect the type of TV attached.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added to check for if the panel supported Panel side scaling.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the DDCReadEDID routine to read EDID from the panel when panel is active.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine ReadFP_EDID to read EDID data from the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMNoMonitor, added code to check if a panel is connected.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMInitRegisters, added code to read the NVRAM to determine if we want to autodetect the TV or force the TV setting.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the routines CheckForPanel and I2CWriteRegister for checking if a panel is attached.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the routines I2CReadBusXBytes and I2CReadByte to read DDC information from the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the routine ChecKFPSideScaling to read the DDC information from the panel and determine if scaling is supported in the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the flag FL_PANELSCALING to set CR1D[5] when panel side scaling is supported.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.08&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/9/99 - Ver. 0.08&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with 32K version of the TSR BIOS hanging when loading.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated all the bank switching routines to reflect new defination of Read/Write Appeture in VgaInit0 and VgaInit1&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the InitBIOS routine, add a conditional compile option around the 32K ROM size patch to compile it into a ROM binary and not a RAM binary. Fixes bug with 32K TSR hanging while loading.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modfied the following bank switch routines to reflect the new Read/Write Appeture bit definations in VgaInit0 and VgaInit1.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMSetBank, OEMSetWBank, OEMGetWBank, OEMSetRBank, OEMGetRBank, OEMIncBank, OEMIncWBank, OEMDecWBank, OEMIncRBank and OEMDecRBank.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/16/99 - Ver. 0.09&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with the size 32K BIOS wasn&amp;#039;t being patched during POST. Bug caused by fix for 32K TSR BIOS hang.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved the patch for the 32K ROM BIOS size into the routine Patch32KROM in OEMPOST.ASM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In init_code, made a call to Patch32KROM when compiling a 32K ROM BIOS only.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine Patch32KROM to patch the ROM size when compiling a 32K ROM BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.10 - 0.19&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.10&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/23/99 - Ver. 0.10&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with some VGA modes not coming up on the TV.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modifed all the VGA 320&amp;times;200 TV modes to use the 320&amp;times;200 TV parameters. Fixes bug with 320&amp;times;200 VGA modes not being displayed on the TV.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixUpTV, Fixed bug in MISC register programming which caused Mode 7 not to display on the TV.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.11&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/2/99 - Ver. 0.11&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with TV subcarrier signal not properly being generated.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified TVData Tables to add BT869 register corrections for Sub-carrier frequency adjustment of NTSC and PAL outputs. Voodoo3 PRS#6772&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added BT869 register writes neccessary to adjust the Sub-carrier frequency so that we will be within 50ppm in NTSC and 25ppm in PAL output. Voodoo3 PRS#6772&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the TVData structure to handle programming the additional Brooktree registers.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.12&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/19/99 - Ver. 0.12&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with not being able to compile a TV BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the routines which read the TV type to read it from the EEPROM instead of Scratch Register 2.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; During POST, EEPROM byte 0 is read to verify valid TV data is present. If TV data isn&amp;#039;t valid, EEPROM byte 0 is written with valid TV data.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified IsNTSCMode, IsPALMode, and GetPALMode to read the TV configuration from the EEPROM byte 0.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified routines which checked if composite TV is active to use the equate FLD_COMPOSITE instead of a hard coded value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the equate FLD_COMPOSITE and CFG_TV_MASK.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Extern defined the I2C routines to fix problem with not being able to compile a Napalm TV BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, removed the code which set Scratch Register 2 to the TV mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, added code to verify that EEPROM byte 0 has valid TV data.  If not valid, EEPROM byte 0 is written with valid TV data.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine I2CWriteAuxEEPROM, for writing data to the EEPROM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified routines which checked if composite TV is active to use the equate FLD_COMPOSITE instead of a hard coded value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.13&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/22/99 - Ver. 0.13&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with 350 scanline modes not being displayed on the TV.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupTVOut, made sure Misc. Output[7:6] are 11b to force Hsync and Vsync to positive.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, changed the default for no CRT, TV, nor LCD attached to CRT only.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.14&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/23/99 - Ver. 0.14&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the Napalm CHIP ID to 07h&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the PUSH and &lt;acronym title=&quot;Post Office Protocol&quot;&gt;POP&lt;/acronym&gt; BX call from the TV code in InitRegisters. This fixes the system hang bug when not doing TV autodetection.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the 18Xh mode numbers to 12Xh. Refer to the document MODELIST.DOC for mode numbers.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.15&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/28/99 - Ver. 0.15&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Redefined the usage of the scratch registers.  Made CR1E for TV data and CR1F for DFP data only. Defination of the scratch register usage is documented in „Scratch Register Usage.XLS“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine GetPanelSize to read the DFP EDID data to determine the size of the attached panel. The size of the panel is stored in scratch register 2, CR1F.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CalcNVRAMchecksum to recalculate the NVRAM checksum after writing data to the NVRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved the CheckForPanel and CheckFPSideScaling routines to OEMPOST.ASM since this is actually once during POST.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine IsPanelSideScaling to return if the attached panel support panel side scaling.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the GetPanelSize routine to read the panel size from SCRATCH_REG3.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the routine I2CReadByte to PUSH ans &lt;acronym title=&quot;Post Office Protocol&quot;&gt;POP&lt;/acronym&gt; AX.  AX needs to be preserved for the Panel sizing routine.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified IsPanelAttached routine to read Scratch Register 2, CR1F, bit 1.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the equates FL_PANEL1280 and FL_PANELSCALING.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the following equates for panel size and panel side scaling:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; SCRATCH_REG3&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; CFG_DFP_SIZE_MASK, CFG_DFP_SIZE_1024, CFG_DFP_SIZE_1280, CFG_DFP_SIZE_1600, FLD_EDID_1280, FLD_EDID_1024, FLD_EDID_800, FLD_PANELSCALING&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the following routines for reading the panel size: DeterminePanelSize and CheckIfSupportedPanelSize.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved the following routines from OEM.ASM into OEMPOST.ASM: CheckFPSideScaling and CheckForPanel.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CalcNVRAMchecksum which calcaultes and writes the Checksum of the NVRAM to byte offset 127. This routine is called after writing the NVRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemNoMonitor, changed thecode to set TV active to use the FLD_TV_ACTIVE equate instead of the 020h value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.16&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/04/99 - Ver. 0.16&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for centering modes on non-scalable DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed the „Panel“ routine to „FixupPanel“&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupPanel, added code to handle progamming the VGA registers for non-scalable panels.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the EXTREGS structure to handle CRTC settings for CR02, CR03, CR15, and CR16 for 1024&amp;times;768 and 1280&amp;times;1024 panels.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Expanded the tblExtRegisters table for CR02, CR03, CR15, and CR16 settings for 1024&amp;times;768 and 1280&amp;times;1024 panels.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.17&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/30/99 - Ver. 0.17&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the Panel EDID routine to use the procedures IsCRTAttached and IsPanelAttached instead of hard coding the routine to read from specific registers.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the panel code in DDCReadEDID to use the routine IsCRTAttached and IsPanelAttached to see if the device is attached before determining to read EDID from the panel or CRT.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine IsCRTAttached to return if the CRT is active.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added code into the FixupPanel return to support programming the CRTC and PLL registers for scaled panels.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine GetDetailedTimingXYRes to parse a panel EDID detailed timing block and return the XY resolution for that detailed timing block.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine ParseAndProgramDetailedTiming to parse a detailed timing block, calculate the CRTC and PLL parameters, and program the CRTC and PLL parameters.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine DoWePatchVGAmodes to return if we need to patch the CRTC parameters for the current VGA mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the routine I2CReadByte to preserve DX.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed the refereces to FLD_CRT to FLD_CRT_ACTIVE.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed the equate FLD_CRT to FLD_CRT_ACTIVE.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.18&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/4/99 - Ver. 0.18&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with panel not being enabling scale panels in DOS after setting CR1F=09h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; For a 32K ROM only, the BIOS needed to update the ROM checksum after discarding the POST. Fixes failure with Elpin test T0920.EXE.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the FixUpPanel routine, moved the code which set REG_VIDINFORMAT to 8000h to the top of the routine. This ensures that REG_VIDINFORMAT is always set when programming the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Patch32KROM, added code to recalculate the BIOS checksum.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.19&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/9/99 - Ver. 0.19&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed problem with halved extended modes (320&amp;times;200, 320&amp;times;240, 400&amp;times;300 and 512&amp;times;384) not being displayed on the DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; NOTE: Currently, the halved modes only use half of the screen horizontally but full screen vertically. The issue with halved extended mode using half of screen horizontally will still need to be addressed.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOSPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created labels for the 640&amp;times;480, 800&amp;times;600, and 1024&amp;times;768 default timings. Fixed up the horizontal blank times for all the 800&amp;times;600 and 1024&amp;times;768 timings.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created externs for the 640&amp;times;480, 800&amp;times;600, and 1024&amp;times;768 VGA tables.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupPanel, &lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for doing 320&amp;times;200, 320&amp;times;240, 512&amp;times;384, and 400&amp;times;300 modes.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the code which patched CR02 to decreament the CR02 value by 1 instead of copying the CR01 value. This helped fixing the problem with halved modes not coming up.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In ParseAndProgramDetailedTimings,&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; CR01, Horizontal Display End, is NOT updated when in doing a halved mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; CR05, Horisontal sync End, is foced to 1Fh for halved modes.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine ProgramCRTCPanelTimings read and program the CRTC timings in BIOSPARM.INC.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine IsHalvedExtMode to return if we&amp;#039;re a halved extende mode mode.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.21 - 0.29&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.21&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10/11/99 - Ver. 0.21&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Merged in all the Napalm 0.20 changes onto the StarTeam Napalm BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for doing 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384 modes centered on a scaling DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created CRTC panel timings for 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384 modes on a scaled DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created externs for the 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384 DFP CRTC timings in OEMDATA.ASM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the FixupPanel routine, for scaled panels only:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Disabled scanline doubling. VIDPROCCFG[4] = 0.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; For the 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384 modes,  loaded the 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384 CRTC timings instead of the 640&amp;times;480, 400&amp;times;300 and 1024&amp;times;768 timings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed problem with modes being too far to the right by skewing the image to the left by writing MiscInit0 [10:08].&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In ProgramCRTCPanelTimings, expanded the CRTC registers which are programmed to include CR12, CR09, CR10, and CR11.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.22&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10/28/99 - Ver. 0.22&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.  To build an DVI, set VGABIOS_OPT=-DBUILD_DVI_BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added support for new BoardConfig DWORD into new OEMConfig structure. BoardConfig return information about the boards memory type, bus type, TV out support, DVI support, CRT support, and if the I2C lines are shorted.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the equates BoardI2CLineShorted, BoardCRTSupport, BoardMemType, BoardTVOutSupport, and BoardDFPSupport.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the word variable OEMConfigVer which is right before the tblOEMConfig label.  OEMConfigVer stores the current version of the OEMConfig table.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the variable „Reserved“ to word align the variable fBoardConfig variable.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the variable fBoardConfig to store the board configuration.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the „XLCD“ references to „DVI“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.23&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 11/30/99 - Ver. 0.23&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Expand the NTSC 640&amp;times;400 and 320&amp;times;200 modes to be full screen on the TV.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified build process to support only have needed one compile flag to build a BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updates the OemConfig structure to return the chip name, oem board name, and version number.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupTVOut, patched the Brooktree TV timings when doing 640&amp;times;400 and 320&amp;times;200.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the following variables from „EQU“ to “=“. This make it possible to change the value of the variable during the compile.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; VARIATION_001, VARIATION_002, VARIATION_003, VARIATION_005, ROM_64K, OPTIMIZED_ROM, FB_High_Priority, TVOUT_BIOS, PAL_BIOS, DVI_BIOS, MCLK_183MHZ, MCLK_166MHZ&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the following variables:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardI2CLineShorted&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardCRTSupport&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; SDRAM_BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardMemType&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardBusType&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardTVOutSupport&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; BoardDFPSupport&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Moved the STR_OEMPRODUCT into each board compile option. Each build option has a unique OEM Product string. The BIOS will now print is the BIOS supports TV or DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the PCI device to 07h for Napalm.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the NTSC TVDATA structure to use the new 640&amp;times;400 and 320&amp;times;200 full screen TV timings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Update the OEMConfig structure to include the VBE product name, OEM Chip name, and OEM BIOS version.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the null terminated strings for Chip name and BIOS Version.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.24&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 12/7/99 - Ver. 0.24&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the panel CRTC timings to fix bug with setmode hanging while in a full screen DOS session in Win98.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the tblExtRegisters table, changed the CR11 panel setting for the following modes to not set CR11[4]. Fixes GPF error when setting these panel modes.&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1024&amp;times;768 panel timings: Updated timings for all 512&amp;times;384 modes and 640x400x16bpp.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1280&amp;times;1024 panel timings: Update timings for modes 07*, 00*, 01*, 02*, 03*, 00/01+, 02/03+ and 07+.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.25&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 12/16/99 - Ver. 0.25&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Overscanned the NTSC 640&amp;times;350 TV parameters to be full screen on the TV. Ratio used were HOC = 13.78 and VOC = 9.88.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the NTSC 640&amp;times;350 TVDATA table entries to support 640&amp;times;350 overscanned parameters.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupTVOut, added code to program the Brooktree TV encoder to do overscanned 640&amp;times;350 NTSC timings.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the PCI device to 07h for Napalm.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.26&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/11/00 - Ver. 0.26&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Create build options for Napalm board Assy# 874 and 872.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the copyright year to 2000.&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; „Copyright (C) 1990-2000 Elpin Systems, Inc.“&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Create build options for Napalm board assy #874, -DBUILD_V5P874 and #872, -DBOARD_V4P872.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the copyright year to 2000.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the copyright year to 2000.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.27&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/15/00 - Ver. 0.27&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Create build options for Napalm board Assy# 879, 880, 881, 882, 883 and 884.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed device ID to 09h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with TRS BIOS hanging.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed memory sizing bug.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed device ID to 09h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the following parameters:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit0 = 00169D25h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit1 = 00046C031h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; MCLK = 02805h&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Find3DFXCard, added check to see if running TRS BIOS before doing SSID check. Will skip SSID check if TRS BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, Changed the DramInit0 mask to not clear DramInit0[26]. Fixed memory sizing error.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.28&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/21/00 - Ver. 0.28&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug in DOS extended mode Write TTY and scrolling function.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; For DFP only, set tmuGBEInit[18]=1 to select a delay of 4. Also set VidInFormat[22] to disable tv_data_scramble. This fixes the problem with wrong colors on the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bugs in bank switching code.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with boot on TV only.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added work-around to memory VBE memory size routines. BIOS VBE memory sise functions will return 16 Meg on board when running on 32 and 64 Meg boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed board designs #872, #882, #883 and #884 from SGRAM to SDRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupPanel, set tmuGBEInit[18]=1 to select delay of 04h. Also set VidInFormat[22] to disable tv_data_scramble to fix the problem with wrong colors on the panel.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemGetWBank and OemGetRBank, fixed bug with not properly getting bits 11 and 10 of the apperture.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the routine CheckIfProduction. Not needed in Napalm.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the build options for board designs #872, #882, #883 and #884 from SGRAM to SDRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In VBEPMI05, code needed to be modified to handle Napalm&amp;#039;s defination of appeture in VGAInit1.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemNoMonitor, removed the call to checkIfProduction from the TV portion of the code.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; SCROLL.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified all the routines which called the bank switching routine to pass DX and not just DL.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In VBE_ReturnControllerInfo and VBEGetmemSize routines, changed the memory size routine to return 16 Meg on board when running on 32 and 64 Meg boards.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.29&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 1/28/00 - Ver. 0.29&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified DFP DDC code to use DDC code instead of the I2C code.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with DDC code not sending a NACK after reading last byte.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Addressed the following PRS:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; #12558 - 320x200x8bpp locks the system when attempting to set 60hz or 65hz in VBETEST.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; #12553 - 1024x768x8@90Hz shows incorrect refresh rate.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; #12555 - 1280x1024x8@65Hz and 70Hz show incorrect refresh rate.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In PatchVertDisplayTime, fixed bug with BIOS being stuck in an infinite loop if vertical total bit 9 = 0. Fixes PRS#12558.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMDDCDisable, changed the AND mask to 09FFBFFFFh to also reset the GPIO port back to 00.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine DDCEnableDFP to setup the DDC calls to the panel. This includes setting up the GPIO port to read DDC data from the DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In SetAbsoluteDotClock, created a software work around to fix the problem with certain PLL settings causing th PLL to not generate the desired output frequency. Address PRS #12553 and #12555.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the routine ReadFP_EDID and calls to this routine.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In DDCStartupSequence, added code to check for an attached panel. If a panel is attached, call DDCEnableDFP to setup the DDC call to read DDC data from the DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In DDCRead, placed a PUSH CX and &lt;acronym title=&quot;Post Office Protocol&quot;&gt;POP&lt;/acronym&gt; CX around call to DDCWaitClockHigh. Fixed bug with a NACK never being sent to the monitor after reading the last byte of DDC data. This enables the BIOS to read DDC data from a Compaq FP720 DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.30 - 0.34&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.30&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/2/00 - Ver. 0.30&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the name of the routine I2CReadByte to DFPReadByte. This routine now uses DDC calls to read DFP EDID data. This change fixes the problem with detecting scaled and non-scaled DFPs and also scaled DFPs now fully supported. Also fixes problem with scaled DFP not coming up in VGA modes.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the calls to I2CReadByte to DFPReadByte.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; DFPReadByte now uses DDC calls to read DFP EDID data.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Renamed all the calls to I2CReadByte to DFPReadByte.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.31&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/2/00 - Ver. 0.31&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with Flight Simulator 5.0 showing garbage when moving around the mouse cursor during a game. Fixes PRS#12642&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemSetWBank, did a PUSH and &lt;acronym title=&quot;Post Office Protocol&quot;&gt;POP&lt;/acronym&gt; EBX at the start and end of the routine.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.32&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/8/00 - Ver. 0.32&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed BIOS chip name string to „VSA 100“.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug in CheckForPanel routine. Would always return panel attached, even though no panel is attached.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with DFP/TV combo BIOS not booting to TV only properly. Fixes PRS#12528.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed unnecessary XLCD code and DFP I2C routines.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the STR_OEMCHIPNAME string to „VSA 100“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the routine I2CWriteRegister_Panel. Not needed since Napalm uses DDC calls.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the extrn for I2CWriteRegister and added an extrn for DDCEnableDFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In CheckForPanel, called the routine DDCEnableDFP to enable access to the DFP. Removed old XLCD code.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.33&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/17/00 - Ver. 0.33&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the PCI Empty low water mark, PCIInit0[6:2], from 0x01 to 0x08.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the BIOS dot clock algorithm for finding PLL settings. This change only effects GTF modes and scaled panel support. This fix addresses PRS#12553 and #12555&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the DEFAULT_PCIINIT0 from 00584FB04h to 00584FB20h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In SetAbsoluteDotClock, removed the software work-around which patch PLL settings to get hi-res modes to work. This work-around was for PRS #12553 and #12555.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; In CalcClockWord, updated the algorithm for finding PLL settings for a specified dot clock.  &lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CheckVCO to validate PLL setting before they are used.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 0.34&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 2/24/00 - Ver. 0.34&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the PCIInit0 setting from 0184FB20 to 01840320h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Forced DramInit0[30] = 1 to always do SDRAM even thou we&amp;#039;re running on SGRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed DEFAULT_PCIINIT0 to 01840320h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made the variable fBoardConfig public.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the routine CheckIfSGRAM to use the variable fBoardConfig instead of testing DramInit0[30].&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, always set DramInit0[30]=1 to force SDRAM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.00 - 1.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.00&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 3/24/00 - Ver. 1.00&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the default DramInit timings for 143MHz MCLK.&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit0 = 00016A9B9h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit1 = 000200031h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; PLLCtl1 (MCLK) = 3A05h = 143MHz&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed problem with some default BIOS modes PLL value causing the mode to „swim“. Updated the PLL values for the following VBE modes:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Extended Text Modes 109h-10Ch, 320&amp;times;200, 320&amp;times;240, and 512&amp;times;384.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Also adjusted the PLL setting for the TV modes.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the sign-on message to report the total amount of memory on board. This includes the memory on the slave chips.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added a 128 Meg memory entry into the memory size string.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; CLKPLL.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Include file which holds the equates of all the VGA and VBE mode clock PLL setting. &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made all the CLK PLL setting into equates and put the equates into CLKPLL.INC.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the memory size strings to include a 128 Meg entry.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the SDRAM and SGRAM memory message strings to say „Total SDRAM “ and &amp;#039;Total SGRAM “.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed memory clock to 143MHz PLLCTRL1=3A05h and DramInit0 = 00016A9B9h and DramInit1 = 000200031h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMSignOn, adjusted the reported memory size depending if we&amp;#039;re a 4-way or 2-way SLI board.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAKEFILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added CLKPLL.INC as part of the dependencies for OEMDATA.ASM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.01&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/5/00 - Ver. 1.01&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed problem with DDC read errors on LG Flatron 759-FT CRT monitor.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the CLK PLL settings for NTSC and PAL 800&amp;times;600.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified TV code to always disable the CRT when TV is active. CRT is disabled by setting MiscInit1[8]=1, Power down CRT DAC.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added code to disable the TV interface, vidInFormat[15] = 0, when TV or DFP is not active. Fixes problem with TV showing garbage when TV is disabled and CRT is enabled.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; CLKPLL.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the PLL setting for 36MHz, PAL 800&amp;times;600 TV clock, and 38.769MHz, NTSC 800&amp;times;600 TV clock.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added additional clock delays to the DDC routines. This fixes the problem with reading DDC information from LG Flatron 759-FT CRT monitor.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMSetRegs, disabled the TV interface when TV or DFP is not active.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMSetRegs, diabled the CRT when TV is active.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.02&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/13/00 - Ver. 1.02&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created a BIOS to run the part at 166MHz. Changed the default MCLK to 166MHz and the DramInit1 setting to 00240031h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the MCLK setting to 166MHz, 720Dh, and the DRAMInit1 setting to 00240031h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.03&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 4/13/00 - Ver. 1.03&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; To improve performance, changed the DramInit0 value to 00116A9A9h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.04&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/03/00 - Ver. 1.04&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Disabled PCI memory retries, PCIInit0[12]=1, to fix problem with dropped pixels in VGA mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated MCLK PLL and DramInit settings.&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Current Settings are as follows:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; MCLK = 166MHz (E721h)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit0 = 001EA9B9h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; DramInit1 = 00240031h&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Disabledd sync on slave chips only on 2-way and 4-way boards.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed PCIInit0 = 01841320h, 166MHz MCLK PLL = E721h, DramInit0 = 001EA9B9h, and DramInit1 = 00240031h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMInitBIOS, added conditional compile code to disable the sync on the slaves chips only on 2-way and 4-way BIOSs.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.05&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/08/00 - Ver. 1.05&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Corrected VPD Checksum to allow for (ICT) Production BIOS programming.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAIN.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed VPD Checksum from 0x85 to 0x79&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.06&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 5/15/00 - Ver. 1.06&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Set VidProcCfg[29:28] = 11 to disable memory optimization.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, set VidProcCfg[29:28] = 11b.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemSetRegs, did a Read-Modify-Write of VidProcCfg. Preserved bits 29-28.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.07&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/5/00 - Ver. 1.07&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed errors in VBE mode timings for 1024&amp;times;768 graphics and 132xXX text modes. Fixes PRS# 14384 and 14386.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; During POST, initilized I/O base address before calling OEMEnableExtentions. Fixes PRS#14303.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOSPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made the sync polarities for 1024&amp;times;768 both negative. Timings now follow the VESA/STB &lt;acronym title=&quot;specification&quot;&gt;spec&lt;/acronym&gt; for this mode. Fixes PRS#14384.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPARM.INC &lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed timing error in horizontal blank end, and horizontal sync start and end. Timings now follows the VESA/STB &lt;acronym title=&quot;specification&quot;&gt;spec&lt;/acronym&gt; for this mode. Fixed PRS#14386.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMInitWakeup, called InitIOBase before calling OEMEnableExtnsions. Fixes PRS#14303.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.08&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/9/00 - Ver. 1.08&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added build for Assy# 0896 (VD5 5500 PCI) at 155MHz. &lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Value of PLLCTRL1 set to 0x3F05 for 155MHz PCI assembly. Will not affect any other assembly.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.09&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/15/00 - Ver. 1.09&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed build options for V5P847 and V5P874. This reflects the current version of the Napalm Board BIOS Names and Build opts.doc.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the build options for V5P847 and V5P874.ROM.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.10 - 1.18&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.10&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/16/00 - Ver. 1.10&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the V5P896 build option to have vidProcCfg[29:28]=00 and all other BIOS builds have vidProcCfg[29:28] = 11.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the flag Build_V5P896. This flag is set only when compiling a V5P896 BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, added conditional compiled code to clear VidProcCfg[29:28]=00 when compiling a V5P896 BIOS. All other BIOSs have VidProcCfg[29:28]=11.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.11&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 6/29/00 - Ver. 1.11&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the modification of the V5P896 build - vidProcCfg[29:28]=00.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Reset the Clock for the V5P869 to 166MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Reset the flags so V5P869 will build at 166MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the following flag and code:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, added conditional compiled code to clear VidProcCfg[29:28]=00 when compiling a V5P896 BIOS. All other BIOSs have VidProcCfg[29:28]=11. (All products have VidProcCfg[29:28]=11.)&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.12&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/21/00 - Ver. 1.12&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created compile flag to disable the display of the copyright message during POST.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the flag DisableCopyrightMsg to display tje copyright message. This flag is enabled by the comple flag “-DTURN_OFF_COPYRIGHT_MSG“.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitBIOS, conditionally compiled the code which display the copyright banner.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.13&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/2/00 - Ver. 1.13&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with some CRT monitors booting monochrome. Fixes PRS#15126.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with booting to TV on BIOSs which has both TV and panel support.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Monitor Sense DAC value, Default_Trigger, from a 18h to 15h. This fixes the problem with some CRT monitors booting monochrome. Fixes PRS#15126.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine DDCWaitClockHigh, decreased the number of retries from 65536 to 256. This decreased the time one had to wait for the TV to boot on a combo TV and DVI BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine CheckForPanel, fixed bug with error checking. This fixed a bug in the combo TV and panel BIOS where the BIOS to booted to the panel when only a TV attached.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed DramInit0 to 0001EA9A9h. Made tRP = 2, row precharge = 3 clocks.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.14&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/4/00 - Ver. 1.14&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated BIOS build options to include the following boards:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P901 - AGP/SD/183 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;/No TV/No LCD/V5-5800&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P899 - AGP/SD/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;/No TV/No LCD/V5-5500&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P896 - PCI/SD/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;/No TV/No LCD/V5-5500&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P902 - AGP/SG/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;/No TV/No LCD/V5-5000&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P899 - AGP/SD/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;/No TV/No LCD/V5-5500&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the following BIOS build options:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P874 - AGP/SG/166/No TV/No LCD/V5-5000&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P847 - PCI/SG/166/No TV/No LCD/V5-5000&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P884 - PCI/SD/166/With TV/With LCD/V4-4500&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the memory clock for the V5P848 BIOS to 183 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added build options for the following boards: V5P901, V5P899, V5P896, V5P902, V5P899.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed build options for the following boards:	V5P874,	V5P847,	V5P884.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the memory clock for the V5P848 to 183 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.15&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/14/00 - Ver. 1.15&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitInfoVars, modified the setmode calls to not clear the screen and only initilize the registers.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the MonitorDetect routine, routine the code which initilizes the RAMDAC to 00h. A setmode call later in POST will re-initilize the DAC to it&amp;#039;s default value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Patch32KRom, optimized the checksum routine to not reload the added ROM during each iteration of the loop. Started the ROM address at 00h and had the LODSB automaticlly increament the address.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.16&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/18/00 - Napalm Ver. 1.16 &amp;amp; Napalm2 Ver. 1.04&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed errors in BIOS default extended mode timings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with BIOS GTF register programming routine.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Condensed the board name strings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added conditional compiled code to only print the string „Supported “ after the board name when compiling a TV and/or LCD BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOSPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the horizontal and vertical sync start and and positions for the following modes: 640&amp;times;400, 640&amp;times;480, 800&amp;times;600, 1024&amp;times;768, 1280&amp;times;1024 and 80&amp;times;60 (Mode 108h).&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the horizontal and vertical sync start and and positions for the following modes: 320&amp;times;200, 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMFixupCRTC, decreased the vertical sync start and end values by one. Only decreaced the horizontal sync start and end value by one when not doing a 1024&amp;times;768 mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CheckIf1024Mode to check if we&amp;#039;re a 1024&amp;times;768 mode. If 1024&amp;times;768 mode, zero flag is set.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.17&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/12/00 - Ver. 1.17&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the BIOS build options to match the Napalm BOM in MRD ver 1.19.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the build option for the V5P901 AGP/SD/166MHz/No TV/No DVI/2 Way.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the MCLK for V5P848 to 166MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added a BIOS option for V4P906 AGP/SD/143MHz/No TV/No DVI/Single chip.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.18&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/14/00 - Ver. 1.18&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with all extended modes coming up corrupted when going into extended mode. Bug is with Napalm2 SGRAMMODE value being programming into Napalm. Fixes PRS#15511.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made the SGRAMMODE register setting coniditional compile for Napalm and Napalm2. Fixes problem with Napalm2 SGRAMMODE setting being used on Napalm. Fixes PRS#15511.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;
&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;daytona_voodoo4-2_voodoo5-2&quot; id=&quot;daytona_voodoo4-2_voodoo5-2&quot;&gt;Daytona (Voodoo4-2 / Voodoo5-2)&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;
&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.00 - 1.05&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.00&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/21/00 - Ver. 1.00&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Initial version of the Napalm2 BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Merged Napalm2 changes into Napalm source. Added to support the strapping option field in Napalm2.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MAKEFILE.N2&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; Napalm2 makefile. Uses the flag “-DBUILD_NAPALM2_BIOS“ to enable Napalm2 build options.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FFF0DATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; NEW FILE&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; File to hold the strapping options data.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the flag „Napalm2_BIOS“ to enable Napalm2 code. By default, Napalm2_BIOS = 0, which disabled Napalm2 options.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created a seperate BIOS version string and device ID for Napalm2.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Patch32KROM, added code to shadow the strapping option data into the 40K region.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.01&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 7/24/00 - Ver. 1.01&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modified the BoardConfigurtion byte to report back DDR memory on board.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created a board configuration for Napalm2. This is PCI/DDR/166/No TV/No LCD V4P872.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated memory sizing routine to support changes in DramInit0[29:27] and tmuGbeInit[27:25].&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made Napalm2 device ID equal 0013h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created a Napalm2 board configuration V4P872, PCI/DDR/166/No TV/No LCD.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Made the Napalm2 device ID 0013h.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the flag DDR_BIOS to flag DDR board. BoardMemType is set to 02h a DDR BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, did a read-modify-write of tmuGbeInit to preserve bits 27 to 25.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OemSigon, called CheckIfDDR to determine is DDR or SDRAM memory. If DDR, print DDR memory size message. Otherwise, print SDRAM memory size message.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added the memory size string szDDR_memory.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added memory size message for 256Meg of memory.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the table tblMemSize to support reporting back 128Meg and 256Meg of video memory.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the routine OemGetMemSize to read tmuGbeInit[27:25] if 32Mbit DDR memory is installed. If so, the memory size is divided by 4.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CheckIfDDR to return is DDR on board.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.02&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/2/00 - Ver. 1.02&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with some CRT monitors booting monochrome. Fixes PRS#15126.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with booting to TV on BIOSs which has both TV and panel support.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Monitor Sense DAC value, Default_Trigger, from a 18h to 15h. This fixes the problem with some CRT monitors booting monochrome. Fixes PRS#15126.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; VESA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine DDCWaitClockHigh, decreased the number of retries from 65536 to 256. This decreased the time one had to wait for the TV to boot on a combo TV and DVI BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the routine CheckForPanel, fixed bug with error checking. This fixed a bug in the combo TV and panel BIOS where the BIOS to booted to the panel when only a TV attached.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed DramInit0 to 0001EA9A9h. Made tRP = 2, row precharge = 3 clocks.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.03&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/14/00 - Ver. 1.03&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Decreased the ampount time it took to execute video POST. For a BIOS with no copyright message, video POST when from ~191 mSec to ~155 mSec.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; INIT.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitInfoVars, modified the setmode calls to not clear the screen and only initilize the registers.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In the MonitorDetect routine, routine the code which initilizes the RAMDAC to 00h. A setmode call later in POST will re-initilize the DAC to it&amp;#039;s default value.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In Patch32KRom, optimized the checksum routine to not reload the added ROM during each iteration of the loop. Started the ROM address at 00h and had the LODSB automaticlly increament the address.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.04&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 8/18/00 - Napalm Ver. 1.16 &amp;amp; Napalm2 Ver. 1.04&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed errors in BIOS default extended mode timings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug with BIOS GTF register programming routine.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Condensed the board name strings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Fixed bug in memory sizing routine.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated PCI device ID to 0Bh.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Put in memory timings for 100MHz MCLK.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added conditional compiled code to only print the string „Supported “ after the board name when compiling a TV and/or LCD BIOS.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; BIOSPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the horizontal and vertical sync start and and positions for the following modes: 640&amp;times;400, 640&amp;times;480, 800&amp;times;600, 1024&amp;times;768, 1280&amp;times;1024 and 80&amp;times;60 (Mode 108h).&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPARM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Updated the horizontal and vertical sync start and and positions for the following modes: 320&amp;times;200, 320&amp;times;240, 400&amp;times;300, and 512&amp;times;384.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMGetMemSize, saved the memory size in AX.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In OEMFixupCRTC, decreased the vertical sync start and end values by one. Only decreaced the horizontal sync start and end value by one when not doing a 1024&amp;times;768 mode.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created the routine CheckIf1024Mode to check if we&amp;#039;re a 1024&amp;times;768 mode. If 1024&amp;times;768 mode, zero flag is set.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In InitRegisters, change the Napalm2 DramInit0 register mask to 072000000h DramInit1 register mask to 0C3000000h. Added Napalm2 code to do a mode set to the memory and to the DLLs on the DDR memory only.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change the Napalm2 memory clock to 100MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Shortened all the STR_OEMPRODUCT strings for the TV and LCD BIOSs.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Removed the words „with“ and „support“ from the string. For example, changed the LCD BIOS from „Voodoo4 4800 with LCD support “ to „Voodoo4 4800 LCD “.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Added memory clock PLL settings for 210MHz, 200MHz, 170MHz, 125MHz and 100MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm2 device ID to 0Bh.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created Napalm2 conditional compiled code for DramInit settings:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; For MCLKs below 143MHz, the following is used:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; DEFAULT_DRAMINIT0 equ 0807FE9A9h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; DEFAULT_DRAMINIT1 equ 040034031h&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; For MCLKs above or equal to 143MHz, the following is used:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; DEFAULT_DRAMINIT0 equ 0807FE9A9h&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level5&quot;&gt;&lt;div class=&quot;li&quot;&gt; DEFAULT_DRAMINIT1 equ 040030031h&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm2 DEFAULT_SGRAMMODE setting to 00002000h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;div class=&quot;spoiler&quot;&gt;&lt;div class=&quot;title&quot;&gt;Version 1.05&lt;/div&gt;&lt;input type=&quot;button&quot; value=&quot;Show&quot; onClick=&quot;c = this.parentNode.getElementsByTagName('div')[1]; if (this.value == 'Show') { c.style.display = ''; this.value = 'Hide' } else { c.style.display = 'none'; this.value = 'Show' }&quot; /&gt;&lt;div class=&quot;content&quot; style=&quot;display: none&quot;&gt;&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; 9/12/00 - Ver. 1.05&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Change MCLK to 143MHz and the DramInit0 timings.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed TV out clock delay to 10 clocks, TmuGbeInit[19:16]=0Ah, for DFP.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Created temporary build options for the following BIOSs:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V4P882-2.ROM PCI/DDR/143/No TV/With LCD | V4-4200&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V5P902-2.ROM AGP/DDR/143/No TV/No LCD/2 Way | V5-5000&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V4P868-2.ROM AGP/DDR/143/No TV/No LCD | V4-4000&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; V4P869-2.ROM AGP/SDR/143/No TV/No LCD | V4-4000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.INC&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm2 MCLK to 143MHz.&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the Napalm2 MCLK 143MHz⇐ DramInit0 to 040034031h.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEM.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; In FixupPanel, changed the TmuGbeInit[19:16] to 0Ah, 10 clock TV clock out delay.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; FFF0DATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Changed the strapping information to:&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; dw 00000h ;0xFFF6/0xFFF7&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; dw 00000h ;0xFFF4/0xFFF5&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; dw 0C400h ;0xFFF2/0xFFF3&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level4&quot;&gt;&lt;div class=&quot;li&quot;&gt; dw 00000h ;0xFFF0/0xFFF1&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMPOST.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Modifed the copyright message to properly display is the BIOS supports DDR or SDR memory.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; OEMDATA.ASM&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level3&quot;&gt;&lt;div class=&quot;li&quot;&gt; Add strings to display total DDR or SDR memory.&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;&lt;/div&gt;
&lt;/div&gt;
</description>
            <author>chosen_one</author>
        <category>wiki:misc</category>
            <pubDate>Sun, 01 Apr 2012 22:01:30 +0200</pubDate>
        </item>
        <item>
            <title>Voodoo5</title>
            <link>http://3dfxbios.cl-rahden.de/doku.php?id=wiki:voodoo_5:voodoo5&amp;rev=1333310378</link>
            <description>
&lt;h1 class=&quot;sectionedit8&quot;&gt;&lt;a name=&quot;voodoo5&quot; id=&quot;voodoo5&quot;&gt;Voodoo5&lt;/a&gt;&lt;/h1&gt;
&lt;div class=&quot;level1&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:vsa100.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:vsa100.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:vsa100.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.tdfx.de&quot; alt=&quot;Quelle: www.tdfx.de&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;p&gt;
&lt;strong&gt;Die Nutzung der hier aufgeführten BIOS-Dateien geschieht auf eigene Gefahr. &lt;br/&gt;

Ich übernehme keine Haftung für eventuelle Schäden an Hard- bzw. Software!&lt;/strong&gt;
&lt;/p&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo5_5000&quot; id=&quot;voodoo5_5000&quot;&gt;Voodoo5 5000&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;agp&quot; id=&quot;agp&quot;&gt;AGP&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:proto_5000_agpx4.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:proto_5000_agpx4.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:proto_5000_agpx4.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.thedodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.thedodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sg-ram&quot; id=&quot;sg-ram&quot;&gt;SG-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5000:agp:v5_5000_agp_1.15.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5000:agp:v5_5000_agp_1.15.rom&quot;&gt;3dfx Voodoo5 5000 AGP SG-RAM 1.15&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 143/143 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.08.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;pci&quot; id=&quot;pci&quot;&gt;PCI&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:proto_5000_pci.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:proto_5000_pci.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:proto_5000_pci.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.thedodgegarage.com/3dfx&quot; alt=&quot;Quelle: www.thedodgegarage.com/3dfx&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sg-ram1&quot; id=&quot;sg-ram1&quot;&gt;SG-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5000:pci:v5_5000_pci_1.00a.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5000:pci:v5_5000_pci_1.00a.rom&quot;&gt;3dfx Voodoo5 5000 PCI SG-RAM 1.00a&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 10.03.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5000:pci:v5_5000_pci_1.00b.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5000:pci:v5_5000_pci_1.00b.rom&quot;&gt;3dfx Voodoo5 5000 PCI SG-RAM 1.00b&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 143/143 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 11.03.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;hr /&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo5_5500&quot; id=&quot;voodoo5_5500&quot;&gt;Voodoo5 5500&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;agp1&quot; id=&quot;agp1&quot;&gt;AGP&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:5500agp.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:5500agp.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:5500agp.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.tdfx.de&quot; alt=&quot;Quelle: www.tdfx.de&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sd-ram&quot; id=&quot;sd-ram&quot;&gt;SD-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.01a_143mhz.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.01a_143mhz.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.01a&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 143/143 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 23.03.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.03e.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.03e.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.03e&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 17.04.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.03h.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.03h.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.03h&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 28.04.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.05.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.05.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.05&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Geflasht auf Preview-Karten für Magazine&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 07.04.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.06.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.06.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.06&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.05.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.12_agp4x.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.12_agp4x.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.12&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; AGP 4x&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 21.07.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.12_agp4x_dvi.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.12_agp4x_dvi.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.12&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DVI-Support (aber &lt;strong&gt;kein&lt;/strong&gt; DVI-Output)&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; AGP 4x&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 21.07.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.15.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.15.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.15&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.08.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.16.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.16.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.16&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 28.08.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:agp:v5_5500_agp_1.18.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:agp:v5_5500_agp_1.18.rom&quot;&gt;3dfx Voodoo5 5500 AGP SD-RAM 1.18&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 14.09.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;pci1&quot; id=&quot;pci1&quot;&gt;PCI&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:5500pci.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:5500pci.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:5500pci.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.tdfx.de&quot; alt=&quot;Quelle: www.tdfx.de&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sd-ram1&quot; id=&quot;sd-ram1&quot;&gt;SD-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.00.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.00.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.00&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Prototyp-BIOS&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 143/143 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 22.03.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.08.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.08.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.08&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 09.06.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.11.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.11.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.11&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 30.06.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.11_dvi.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.11_dvi.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.11&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DVI-Support&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 30.06.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.15.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.15.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.15&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.08.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.16.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.16.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.16&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 28.08.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:5500:pci:v5_5500_pci_1.18_dvi.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:5500:pci:v5_5500_pci_1.18_dvi.rom&quot;&gt;3dfx Voodoo5 5500 PCI SD-RAM 1.18&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; DVI-Support&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 25.06.2000 (Neueste Version - nicht das neuste BIOS)&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;hr /&gt;

&lt;p&gt;
&lt;br/&gt;

&lt;/p&gt;

&lt;/div&gt;

&lt;h3&gt;&lt;a name=&quot;voodoo5_6000&quot; id=&quot;voodoo5_6000&quot;&gt;Voodoo5 6000&lt;/a&gt;&lt;/h3&gt;
&lt;div class=&quot;level3&quot;&gt;

&lt;/div&gt;

&lt;h4&gt;&lt;a name=&quot;agp2&quot; id=&quot;agp2&quot;&gt;AGP&lt;/a&gt;&lt;/h4&gt;
&lt;div class=&quot;level4&quot;&gt;

&lt;p&gt;
&lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/detail.php?id=wiki%3Avoodoo_5%3Avoodoo5&amp;amp;media=upload:bilder:6000agp.jpg&quot; class=&quot;media&quot; title=&quot;upload:bilder:6000agp.jpg&quot;&gt;&lt;img src=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:bilder:6000agp.jpg&quot; class=&quot;media&quot; title=&quot;Quelle: www.tdfx.de&quot; alt=&quot;Quelle: www.tdfx.de&quot; /&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;/div&gt;

&lt;h5&gt;&lt;a name=&quot;sd-ram2&quot; id=&quot;sd-ram2&quot;&gt;SD-RAM&lt;/a&gt;&lt;/h5&gt;
&lt;div class=&quot;level5&quot;&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.27_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_15.01.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.27_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_15.01.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 0.27 [Rev.1 Intel Rev.A0/A1/A #0700-1900]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 33212E45A9C046628F59036CBB1A61A2&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 15.01.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.28_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_21.01.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.28_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_21.01.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 0.28 [Rev.1 Intel Rev.A0/A1/A #0700-1900]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 62CD3CA93F70B5641C9BFE642E4A3D42&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 21.01.2000  &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.29_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_03.02.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.29_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_03.02.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 0.29 [Rev.1 Intel Rev.A0/A1/A #0700-1900]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: C6BB81236FD88A8A720EB2166C141B4A&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 03.02.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.32_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_08.02.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_0.32_rev.1_intel_rev.a0-a1-a_0700-1900_100mhz_08.02.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 0.32 [Rev.1 Intel Rev.A0/A1/A #0700-1900]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 100/100 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 01C53A91C4393C343008A11438E82120&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 08.02.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.11_rev.2_hint_rev.a2_2600_166mhz_30.06.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.11_rev.2_hint_rev.a2_2600_166mhz_30.06.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.11 [Rev.2 HiNT Rev.A2 #2600]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 1B23F86CCFD04E4AC70E5277A7083931&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 30.06.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.11_rev.2_hint_rev.a2_2600_166mhz_30.06.2000_2.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.11_rev.2_hint_rev.a2_2600_166mhz_30.06.2000_2.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.11 [Rev.2 HiNT Rev.A2 #2600]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 6557BEC45B6CD1C0E6740A8F48895370&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 30.06.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.3_hint_rev.a3_3400_166mhz_18.08.2000_2.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.3_hint_rev.a3_3400_166mhz_18.08.2000_2.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.16 [Rev.3 HiNT Rev.A3 #3400]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 44E12E12845CD45594DA46FB5C0D97F1&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 18.08.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a_3700_166mhz_18.08.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a_3700_166mhz_18.08.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.16 [Rev.4 HiNT Rev.A #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: BCCBFB5485B7D8BD12EB10BA260F1BA2&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 18.08.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a_3700_166mhz_24.08.00.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a_3700_166mhz_24.08.00.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.16 [Rev.4 HiNT Rev.A #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 42C3BF9D2CD53EE20136A68E834CAC9D&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 24.08.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a3_3700_166mhz_18.08.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.16_rev.4_hint_rev.a3_3700_166mhz_18.08.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.16 [Rev.4 HiNT Rev.A3 #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: D1CEE1059968F4866CC7CC876ED5705D&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 18.08.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a_3700_166mhz_06.10.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a_3700_166mhz_06.10.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.18 [Rev.4 HiNT Rev.A #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 30F70D81E6EF48D27FD4233CDF75CB6F&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 06.10.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a_3700_166mhz_26.09.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a_3700_166mhz_26.09.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.18 [Rev.4 HiNT Rev.A #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: 5B4897CE9FD6EA2D1666F0F7D64D6D13&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 26.09.2000 &lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li class=&quot;level1&quot;&gt;&lt;div class=&quot;li&quot;&gt; &lt;a href=&quot;http://3dfxbios.cl-rahden.de/lib/exe/fetch.php?media=upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a3_3700_166mhz_05.10.2000.rom&quot; class=&quot;media mediafile mf_rom&quot; title=&quot;upload:voodoo_5:6000:agp:sd-ram:v5_6000_agp_sd-ram_1.18_rev.4_hint_rev.a3_3700_166mhz_05.10.2000.rom&quot;&gt;3dfx Voodoo5 6000 AGP SD-RAM 1.18 [Rev.4 HiNT Rev.A3 #3700]&lt;/a&gt;&lt;/div&gt;
&lt;ul&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; Taktung: 166/166 &lt;acronym title=&quot;Megahertz&quot;&gt;MHz&lt;/acronym&gt;&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; MD5-Hash: F110407FED748D204A7FB9CBA9474A2E&lt;/div&gt;
&lt;/li&gt;
&lt;li class=&quot;level2&quot;&gt;&lt;div class=&quot;li&quot;&gt; 05.10.2000&lt;/div&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;

&lt;/div&gt;
</description>
            <author>chosen_one</author>
        <category>wiki:voodoo_5</category>
            <pubDate>Sun, 01 Apr 2012 21:59:38 +0200</pubDate>
        </item>
    </channel>
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